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I'm Saar Drimer, an electronics craftsman.
Hello! This is my CV.
I'm a hardware engineer interested in exploring new ways to design, and interact with, electronics. I'm motivated by fresh new ideas that challenge engineering traditions in order to create clever 'things'. I cook, do artistic things, garden, and build. Dog lover.
Work experience
Boldport: founder
October 2010 — Present
https://boldport.com
Current:
- Software development for electronics, and related, products.
- Technical writing.
Past:
- Designing electronics with visual and interactive elements, exploring the circuit board medium and electronic components to create products that evoke curiosity, promote engagement and encourage creativity.
- Operated the successful Boldport Club, a monthly subscription of electronics projects that we sent to over 500 members worldwide.
- Development and maintenance of PCBmodE, an open source circuit design tool that provides complete circuit board design freedom.
- Operating the Boldport Studio, designing custom creative electronics for companies.
Eurocircuits: technical writer, editor, research, marketing
October 2020 — June 2025
- Writing about PCB design, manufacturing, and technology.
- General editorial with emphasis on effective communication of Eurocircuits' capabilities.
Elektor International: technical author
March 2021 — October 2021
BERG London: hardware design contractor
August 2012 — November 2012 & July 2013 — October 2013
London, UK
- Two engagements to design the electronics for a Bluetooth connected consumer product for a large household brand BERG client. Researched and implemented a robust and new colour detection mechanism as part of the product's operation.
Argon Design: Principal Engineer
January 2012 — September 2012
Cambridge, UK
- Design a mobile-phone-like device for a client and delivered the first functional unit. Performed circuit design, schematic capture, board layout, build, project management; embedded software.
University of Cambridge: Research Associate
November 2009 — June 2010
- Post-doc in the Computer Architecture group, Computer Laboratory. Performed multi-processor architecture simulation on an FPGA-based platform together with source code management and integration.
Xilinx, Design Engineer II: Advanced Product Division (Virtex FPGAs)
April 2002 — August 2005
San Jose, California
- Designed characterization and verification boards for new silicon.
- Designed a demonstration platform for FPGA security (LogicVault).
- Gate-level verification and development for new FPGAs.
- Developed and deployed large experiments to detect the effects of radiation on FPGA configuration memory cells (Rosetta).
Kinaare Networks: Engineering Intern
Summer 2000
Sunnyvale, California
- Part of a team designing an RF product (IEEE 802.11b, QoS), CEBus modules, and power supplies.
Education
PhD Computer Science,
Department of Computer Science and Technology,
Cambridge University
October 2005 — October 2009
Academic adviser: Dr Markus G. Kuhn
Industry adviser: Austin Lesea
- Dissertation: Security for volatile FPGAs.
- Full scholarship from Xilinx Inc.
- Developed a security protocol for remote update of FPGA configurations.
- Developed open source HDL implementations of efficient AES designs.
- Discovered and demonstrated several security vulnerabilities of the EMV payment system.
BSc Computer Engineering,
University of California at Santa Cruz
October 1998 — June 2002
- Received Comprehensive Honors and School of Engineering Dean's Award.
- Developed an FPGA-based platform for demonstrating image processing algorithms as final project.
Speaking or media
May 2016 — NMI Open Source Conference
Sailing the open seas.
- Experiences and lessons from operating an open-source minded business.
February 2016 — Free and Open Source Software Developers European Meeting (FOSDEM)
1. The future of what we call EDA may not be so bleak.
- Thoughts on where we're headed with the EDA industry and why one possible future looks good.
2. PCBmodE, a PCB design tool with a twist.
- What PCBmodE is, what it isn't, where it's been, and where it is going.
June 2011 — Open Source Hardware User Group (OSHUG)
Building open, communicating communities.
- Reporting on my work to ease hardware design and creating a community of developers.
October 2010 — Institution of Engineering and Technology (IET)
Chip&PIN — notes on a dysfunctional security system.
- A summary of my findings on the security of Chip£PIN during my PhD.
February 2010 — BBC Newsnight programme
- Segment reporting on our Chip&PIN is broken paper where we describe and demonstrate how cards could be used without knowing the PIN.
February 2008 — BBC Newsnight programme
- Segment reporting on design and certification flaws we discovered in several PIN entry devices, and their security implications.
February 2007 — BBC Watchdog programme
- Segment reporting our research and demonstration of a successful ‘relay attack’ against the Chip&PIN payment system.
Selected publications
- Chip and PIN is broken
S.J. Murdoch, S. Drimer, R. Anderson, and Mike Bond
- DSPs, BRAMs and a pinch of logic: extended recipes for AES on FPGAs
S. Drimer, T. Güneysu, and C. Paar
ACM Transactions on Reconfigurable Technology and Systems, Issue 3, Volume 1, 2010-01.
Paper,
source code.
- Failures of tamper-proofing in PIN entry devices
S. Drimer, S.J. Murdoch, and R. Anderson
IEEE, Security & Privacy magazine (invited), 2009-11.
Publication.
- Secure proximity identification for RFID
G.P. Hancke and S. Drimer
Book chapter in Security in RFID and Sensor Networks, Zhang
and Kitsos (Eds), Auerbach Publications, Taylor & Francis
Group, 2009-03.
- A protocol for secure remote updates of FPGA configurations
S. Drimer and M. G. Kuhn
5th International Workshop on Applied Reconfigurable
Computing, 2009-03.
Paper.
- Optimised to fail: card readers for online banking
S. Drimer, S.J. Murdoch, and R. Anderson
13th International Conference on Financial Cryptography and
Data Security, 2009-02.
Paper,
video.
- Thinking inside the box: system-level failures of tamper
proofing
S. Drimer, S.J. Murdoch, and R. Anderson
- DSPs, BRAMs and a pinch of logic: new recipes for AES on
FPGAs
S. Drimer, T. Güneysu, and C. Paar
IEEE Symposium on Field-Programmable Custom Computing
Machines, 2008-04.
Paper,
source code.
- Keep your enemies close: distance bounding against smartcard
relay attacks
S. Drimer and S.J. Murdoch
16th USENIX Security Symposium, 2007-08.
Paper,
video.
Awarded '
Best Student Paper'.
- Authentication of FPGA bitstreams: why and how
S. Drimer
3rd rd International Workshop on Applied Reconfigurable
Computing, 2007-03.
Paper.
- The Rosetta experiment: atmospheric soft error rate testing in
differing technology FPGAs
A. Lesea, S. Drimer, J. Fabula, C. Carmichael, and P. Alfke
IEEE Transactions on Device and Materials Reliability
(invited), 2005-09.
Paper.
Technical reports
- Security for volatile FPGAs
S. Drimer
- Protecting multiple cores in a single FPGA design
S. Drimer, T. Güneysu, M.G. Kuhn, and C. Paar
- Volatile FPGA design security – a survey
S Drimer
Patents
- Random sequence generation using alpha particle emission
S. Drimer
US Patent
7550858, granted 2009-06, filed 7/2005.
- True random number generator and method of generating true
random numbers
S. Drimer
US Patent
7502815, granted 2009-03, filed 2004-02.
- Radio frequency identification (RFID) and programmable logic
device (PLD) integration and applications
S. Drimer
US Patent
7429926, granted 2008-09, filed 2005-06.
- Circuit for and method of implementing a plurality of circuits
on a programmable logic device<
S. Drimer, J. Moore, and A. Lesea
US Patent
7408381, granted 2008-08, filed 2006-02.
- Total configuration memory cell validation built in self test
(BIST) circuit
S. Drimer
US Patent
7409610, granted 2008-08, filed 2005-07.
- Method of measuring the performance of a transceiver in a
programmable logic device
A. Lesea and S. Drimer
US Patent
7218670, granted 2007-05, filed 2003-11.
Last edited: 2025-10-03