Verilog AES source code, by Saar Drimer

The source code available below is associated with the following documents:

- Saar Drimer: "Security for volatile FPGAs", PhD dissertation, 9/2009

- Saar Drimer, Tim Guneysu and Christof Paar: DSPs, BRAMs and a pinch of logic: extended recipes for AES on FPGAs, ACM Transactions on Reconfigurable Technology and Systems, Issue 3, Volume 1, 3/2010

Please see README.TXT for license information, and execution instructions:

AES Verilog code version 1.0 (2009/08/12):

last edited 2009/12/08